1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a DRAM with memory cells each consisting of a MOS transistor and a trench-stacked capacitor in which information is stored.
2. Description of the Prior Art
In early DRAMs of the one-MOS transistor/one-capacitor type, planar capacitors were used. For the purpose of reducing memory cell space compared with planar capacitor DRAMs, trench capacitor DRAMs have appeared.
General structure of trench capacitor memory cells comprises a n-channel MOS transistor and a trench capacitor at a p-type silicon substrate. The MOS transistor consists of a gate electrode serving also as word line, a gate oxide film, and source and drain regions of the first n.sup.- layer. The drain region is connected to a bit line through bit contact hole. The trench capacitor is built in a trench at the surface of p-type silicon substrate by forming the second diffused n.sup.- layer to be a storage node electrode on the exposed surface (trench wall) of the p-type silicon substrate, a dielectric film placed thereover, and a cell plate electrode formed over the dielectric film. At the upper end of the trench, the source region is contiguous to the second diffused n.sup.- layer. Separation between the elements of the adjacent memory cells is achieved by a p.sup.+ -channel stopper region (herein the "p.sup.+ " represents higher p-type impurity concentration than that of the p-type silicon substrate) and field oxide film.
In this structure, there is a junction between the p.sup.+ -channel stopper region and the second diffused n.sup.+ layer of the trench capacitor, and the current leakage across the junction presents problem with degradation of the stored-information retentivity.
There are methods for preventing junction leakage, for example, by forming a diffused n.sup.- layer as the storage node electrode, and by using the p-type silicon substrate itself as storage node electrode. For example, when a memory cell drive supply voltage of 5 V is used (referred to as 5 V-supply, hereinafter), the cell plate is supplied with 2.5 V. The information-write bit line of the memory cell is supplied with 5 V. For example, assuming the MOS transistor of the memory cell to have a threshold voltage of 1.0 V, the storage node electrode is raised to about 4 V for the information write. With these methods, therefore, spacings up to 0.8 .mu.m between the adjacent trench capacitors result in occurrence of a depletion layer from the storage node electrodes, and in turn induction of punchthrough between the neighboring trench capacitors. This causes another problem of difficult retention of stored information. To 5 V-supplied trench capacitor DRAMs, therefore, the width of the separation region between the adjacent elements (referred to as element separating region, hereinafter) is an impeding factor against microminiaturization. A further problem is associated with becoming liable to produce soft error due to .alpha.-particles. Besides even if the spacing between elements is great enough to impede occurrence of punchthrough, the occurrence of depletion layer from the information-storage node electrode leads to reduction of effective capacitance of the capacitor.
For example, Japanese Laid-open Patent Application No. Sho.59-191,373 discloses a trench-stacked capacitor DRAM for solving the problem of the punchthrough phenomenon associated with trench capacitor DRAMs. The trench-stacked capacitor memory cell described in this patent specification is constructed of a n-channel MOS transistor and a trench-stacked capacitor built at the surface of a p-type silicon substrate. The MOS transistor of which the structure is almost the same as the MOS transistor of the trench capacitor DRAM. The trench-stacked capacitor extends deep into a U-shaped trench formed at the p-type silicon substrate, and the surface of it is covered with an insulting film. It is a structure consisting of a storage node electrode, a dielectric film, and a cell plate electrode stacked, the succeeding over the surface of the preceding. The storage node electrode is connected to a source region through a node contact hole reaching the top face of the source region. The structure according to this patent specification is accompanied by no occurrence of punchthrough between capacitors due to the depletion layer from storage node electrode, which cancels restriction to the separation spacing between elements, and effects microminiaturization.
In addition it is disclosed in Japanese Laid-Open Application No.Sho.60-126861 that a diffused p.sup.+ layer is provided at the exposed surface of a p-type silicon substrate as the result of forming a V-shaped trench at this substrate, and thereby reliable prevention of punchthrough occurrence between capacitors is obtainable.
The above discussion is true of preventing punchthrough between capacitors in the 5 V-supplied DRAM but not referred to the MOS transistor of the memory cell. A proposal of reducing junction leakage between the p.sup.+ -channel stopper region of the element-separating region junction and the source and drain regions of the MOS transistor was made, and brings about a tendency to produce punchthrough between the adjacent MOS transistors.
With microminiaturization of DRAMs, lower supply voltage is used. For example, using 0.6 .mu.m feature design rules, memory cell drive supply voltage is 3.3 V. Correspondingly 1.65 V is applied to the cell plate electrode and 5 V to the information-write bit line of the memory cell. For example, assuming the threshold voltage of the memory-cell MOS transistor to be 1.0 V, the storage node electrode is supplied with about 2.3 V by the information writing. Building of trench capacitor DRAM using this design rules enables to prevent punchthrough between the adjacent trench capacitors due to occurrence of depletion layer from the storage node electrode, only if the spacing between the adjacent trench capacitors is about 0.4 .mu.m (for example, the element separating region has a minimum width of 0.6 .mu.m). It however is impossible to reduce the effective capacitance of the capacitor due to the occurrence of depletion layer from the information-stored node electrode.
In the trench-stacked capacitor DRAM, a node contact hole is required for connection between the storage node electrode and the source electrode. The existence of node contact hole like this in the trench-stacked capacitor DRAM becomes larger barrier with microminiaturization of DRAM against reduction of memory cell space.